Reducing ESL in power distribution networks
KEY TAKEAWAYS:
- Low ESL helps capacitors stay effective at high frequencies
- New capacitor designs reduce ESL without losing capacitance
- Fast SiC and GaN switching makes low ESL more critical
Before looking at low-equivalent series inductance (ESL) capacitor architectures, it helps to understand how ESL changes capacitor behavior across frequency and why it matters in a power distribution network.
Every capacitor has a parasitic inductance caused by internal electrodes, leads and terminations, referred to as ESL. This adds to any inductances introduced by the PCB itself.
Parasitic inductance introduced by the PCB layout is especially problematic in high-current switching paths. Keeping these paths short and close to the top layer of the PCB can help reduce loop inductance. Once board-level inductance is controlled, capacitor ESL becomes a more visible and manageable part of the power network design.
Because all capacitors have some ESL and its counterpart, equivalent series resistance (ESR), they can be modeled as an RLC network. At a frequency specific to that network, the inductive and capacitive reactances are equal, leaving the ESR to dominate the impedance. This is referred to as the self-resonant frequency (SRF). Below this frequency the component behaves mainly as a capacitor; above it, the inductive behavior increasingly dominates and the capacitor becomes less effective at decoupling high-frequency noise.
ESL is strongly influenced by the path the current takes through the device and, in general, shorter current paths mean lower ESL. Smaller devices often have lower ESL, but capacitance is also determined by dielectric material, layer count, electrode area and voltage rating. This is why low-ESL designs focus on shortening the current path while preserving the active capacitance structure.
Lowering ESL through design innovation
Multi-layer chip capacitors (MLCCs) are typically longer on one side, with the contacts on the shorter sides. One successful approach to reducing ESL in MLCCs is to move the contacts to the longer sides, thereby shortening the current path without reducing capacitance.
Low-inductance chip capacitors (LICCs), also known as reverse-geometry capacitors (RGCs), employ this technique to reduce ESL, sometimes by as much as 60%. Flipping the geometry changes the capacitor’s nomenclature, so a 1206 becomes a 0612. Kyocera AVX data shows that a 1206 MLCC has an ESL of 1200pH, which drops to around 400pH when it is flipped and becomes a 0612 LICC.
Placing multiple MLCCs in parallel reduces the effective series resistance (ESR) and can also reduce effective inductance when the layout keeps the current loops short and balanced. The interdigitated capacitor (IDC) takes the LICC concept further by configuring multiple capacitive elements in a single, multi-terminal device with alternating current paths. This creates opposing current loops that drastically reduce ESL. An IDC specifically targets decoupling and takes up less space than a comparable MLCC array.
The next generation of architectural innovation is the land grid array (LGA) capacitor. Using advanced manufacturing processes, the LGA orients internal terminals vertically, reducing current-loop area without simply shrinking the device. This helps overcome the trade-off between low ESL and usable capacitance. In addition, IDCs can have multiple terminals, while LGAs have far fewer, resulting in more reliable solder joints and easier layout.
Low ESL capacitors for power networks
According to Kyocera AVX, multi-terminal LGAs are now appearing on the market that will appeal to design teams developing power distribution networks.
Wide bandgap (WBG) materials, including silicon carbide (SiC) and gallium nitride (GaN), are being chosen over silicon MOSFETs and IGBTs in high-power applications. The DC link is a critical function in AC/DC converters and inverters, sitting between the AC front end and the inverter or converter output stage.
Moving to WBG puts more pressure on the DC link capacitor, which acts as both a low-impedance path for high-frequency switching currents and an energy reservoir between AC cycles. Because SiC and GaN transistors switch faster than silicon MOSFETs and IGBTs, the ESL of the DC link and local decoupling capacitors become more critical.
Any inductance in the link can contribute to sharp voltage spikes as the power transistors turn on and off. Placing low-ESL ceramic capacitors close to the transistors helps decouple high-frequency switching currents. Higher switching frequency can also reduce the required bulk capacitance because the ripple-current period is shorter. This can make the overall design smaller and reduce passive component cost, but only if the capacitor network has sufficiently low ESL and ESR.
Another development involves embedding capacitors directly into the package, close to the semiconductor die. This shortens current paths and allows parallel capacitance to be placed nearer to the switching device, helping minimize parasitic inductance.
Expert advice is available
Avnet works with leading capacitor suppliers, giving its field application engineers visibility into the latest low-ESL technologies and where they fit in real power designs. If your engineering team is developing a power supply or power distribution network, Avnet can help identify capacitor options that support performance, reliability and layout goals.
