DC bias derating in multi-level ceramic capacitors is a focus area for suppliers
KEY TAKEAWAYS:
- Dielectrics are evolving, with steady progress toward more bias tolerance
- Mitigation techniques provide real-world benefits
- Design support, including simulation tool guidance, is available from Avnet
Modern applications, led most notably by electric vehicles (EVs) and advanced driver assistance systems (ADAS), have exerted some pressure on capacitor manufacturers to deliver higher capacitance in smaller packages. The trend specifically impacts multi-layer ceramic capacitors (MLCCs).
Suppliers are accommodating the demand, but it comes with trade-offs. To reduce the overall volume, the capacitors now have thinner dielectric layers. This is the active ingredient in MLCCs, and the significance of thinner layers is more pronounced DC bias derating.
All dielectric materials lose charge capacity when the dipoles’ charge vectors are aligned. This is caused by the electric field generated by the voltage applied across the device. Increasing the intensity of the field eventually leads to polarization saturation, and exceeding the voltage rating results in dielectric saturation. Molecular distortion and crystal lattice dislocation follow, leading to even lower capacitance. This phenomenon is referred to as DC bias derating.
DC bias derating is almost exclusively an artifact of capacitors constructed from Class II and Class III dielectrics. This includes X5R, X7R, X6S and Y5V but extends to any device constructed using barium titanate (BaTiO3). As a ferroelectric material, the crystalline structure of BaTiO3 is affected by the magnitude of the DC voltage. Contrastingly, Class I dielectrics are paraelectric and effectively immune to the DC bias effect.
The solution many manufacturers are pursuing involves changing how BaTiO3 behaves when the DC voltage across it is near the maximum rated voltage. And the techniques they’re looking at have similarities to the semiconductor industry.
What’s going on inside an MLCC?
The ceramic structure is made up of grains, individual crystalline particles. Dipoles of these grains align under a DC bias, referred to as domains. This alignment causes the derating effect.
Research has shown that introducing rare-earth or transition-metal dopants alters the grain’s structure, causing the domains to break into smaller structures that resist reorientation under a DC bias. This stabilizes the capacitance. Other research has focused on a core-shell dielectric architecture, where the grain’s core is surrounded by a thinner shell that absorbs the electric field and reduces the bias effect.
Summary of developments to mitigate DC bias dielectric over the past five years
| Approach | Implications | Trade-offs |
|---|---|---|
| Grain/domain refinement using doping | Breaks long-range ferroelectric order into nano-domains, reducing dipole pinning under bias | Slightly lower peak dielectric constant vs undoped material |
| Core-shell grain architecture | Low-permittivity shell buffers electric field around high-K core | Added process complexity in powder synthesis |
| Nanoparticle/atomization powder processing | Finer, less agglomerated powder, more uniformity, stable dielectric layers | Primarily benefits high-voltage, high-capacitance parts |
| Thicker dielectric layers, larger case or higher voltage rating | Weaker field per volt across a thicker layer | Larger footprint, higher cost, more board space |
| Extending Class I into higher voltages | Avoids ferroelectric dielectric entirely | Lower volumetric capacitance than Class II |
| Non-ceramic alternatives (polymer, film) | No ferroelectric voltage coefficient | Larger size, different Equivalent Series Resistance/frequency behavior, higher cost in some cases |
Practical measures and design guidance
Although materials science has advanced, established mitigation techniques are still important. As Avnet’s field application engineers can testify, typical measures include choosing a capacitor with a higher voltage rating than strictly necessary for the design. Choosing a larger case size would likely mean thicker dielectric layers. Using multiple lower-voltage capacitors in parallel also works, if space and cost allow.
Incremental improvements in dielectric materials science have occurred over the last five years or so, and ongoing research will, no doubt, reach production in the next several years. Alternatives to ceramic capacitors, such as tantalum-polymer and film capacitors, are also gaining commercial traction as substitutes in bias-sensitive power applications.
Recent research into on-chip decoupling capacitors with a bias linearity better than MLCCs uses a complementary metal oxide semiconductor (CMOS)-friendly process that is also compatible with discreet processes. Interested engineers could also look for developments around superparaelectric relaxor ceramics and antiferroelectric energy storage materials, which show promise in research projects. These could eventually deliver greater gains in the development of bias-tolerant dielectrics.
If you are developing a power supply and need guidance choosing the best capacitor for your application, contact your local Avnet representative to talk to our field application engineers. For more tips, check out our article, “Six capacitor design takeaways for power supply engineers.”
