MC100EP195FAR2G
3.3 V ECL Programmable Delay Chip
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RoHS 10 Compliant -
Tariff Charges
- Maximum Input Clock Frequency >1.2 GHz Typical
- Programmable Range: 0 ns to 10 ns
- Delay Range: 2.2 ns to 12.2 ns
- 10 ps Increments
- PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V
- IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels
- A Logic High on the EN Pin Will Force Q to Logic Low
- D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels
- VBB Output Reference Voltage
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Programmable Delay | ||
| null | ||
| MSL 2 - 1 year | ||
| 32 Pins | ||
| 1024 Taps | ||
| 10 Taps | ||
| 85 °C | ||
| -40 °C | ||
| null | ||
| null | ||
| 3.6 VDC | ||
| 3 VDC | ||
| 12.2 ns/ft |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390070 |
| Schedule B: | 8542390060 |
Factory Lead Time: