S9S12ZVL32F0VLF

The MC9S12ZVL-Family is an automotive 16-bit microcontroller family using the 180nm NVM + UHV technology that offers the capability to integrate 40V analog components. This family reuses many features from the existing S12 portfolio. The particular differentiating features of this family are the enhanced S12Z core and the integration of “high-voltage” analog modules, including the voltage regulator (VREG) and a Local Interconnect Network (LIN) physical layer. The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The MC9S12ZVL-Family delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of existing S12 families. The MC9S12ZVL-Family is available in 48-pin, 32-pin LQFP and 32-pin QFN-EP. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. The MC9S12ZVL-Family is a general-purpose family of devices suitable for a wide range of applications. The MC9S12ZVL-Family is targeted at generic automotive applications requiring LIN connectivity. Typical examples of these applications include switch panels and body endpoints for sensors.

• S12Z CPU core
• 32, 16 or 8 KB on-chip flash with ECC
• 128 byte EEPROM with ECC
• 1024 or 512 byte on-chip SRAM with ECC
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range
• 4-20 MHz amplitude controlled pierce oscillator
• Internal COP (watchdog) module
• analog-to-digital converter (ADC) with 10 -bit resolution and up to 10 channels available on external pins and Vbg (bandgap) result reference
• One serial peripheral interface (SPI) module
• One serial communication interface (SCI) module with interface to internal LIN physical layer transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)
• Up to one additional SCI (not connected to LIN physical layer)
• One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard
• 6-channel timer mod