S912XEG384BVAL

The MC9S12XE-Family of microcontrollers is a further development of the S12XD-Family including new features for enhanced system integrity and greater functionality. These new features include a Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship MC9S12XE100. The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of compatibility between the S12XE and S12XD families. The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor which is programmable in “C” language and runs at twice the bus frequency of the S12X with an instruction set optimized for data movement, logic and bit manipulation instructions and which can service any peripheral module on the device. The new enhanced version has improved interrupt handling capability and is fully compatible with the existing XGATE module. The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM, eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8- channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8- channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit standard timer module (TIM). The MC9S12XE-Family uses 16-bit wide accesses

• 16-Bit CPU12X
  • Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed
  • Enhanced indexed addressing
  • Access to large data segments independent of PPAGE
• INT (interrupt module)
  • Eight levels of nested interrupts
  • Flexible assignment of interrupt sources to each interrupt level.
  • External non-maskable high priority interrupt (XIRQ)
  • Internal non-maskable high priority Memory Protection Unit interrupt
  • Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts
• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)
  • Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces
  • Each chip select output can be configured to complete transaction on either the time-out of one of the two wait state generators or the de