PIC24HJ128GP506A-H/MR

The PIC24HJXXXGPX06A/X08A/X10A device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes). This makes these families suitable for a wide variety of high-performance digital signal control applications. The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application. The PIC24HJXXXGPX06A/X08A/X10A device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control. The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24HJXXXGPX06A/X08A/X10A Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24HJXXXGPX06A/X08A/X10A devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24HJXXXGPX06A/X08A/X10A devices.

• Operating Conditions
• 3.0V to 3.6V, -40°C to +150°C, DC to 20 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 40 MIPS
• Core: 16-bit PIC24H CPU
• Code-efficient (C and Assembly) architecture
• Single-cycle mixed-sign MUL plus hardware divide
• Clock Management
• ±2% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast wake-up and start-up
• Power Management
• Low-power management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1.35 mA/MHz dynamic current (typical)
• 55 µA IPD current (typical)
• Advanced Analog Features
• Two ADC modules:
  • Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H
  • 18 analog inputs on 64-pin devices and up to 32 analog inputs on 100-pin devices
• Flexible and independe