PIC24FJ32GA002-I/SS

This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ64GA004 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don’t require the numerical processing power of a digital signal processor. Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) A 16-element working register array with built-in software stack support A 17 x 17 hardware multiplier with support for integer math Hardware support for 32 by 16-bit division An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’ Operational performance up to 16 MIPS POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ64GA004 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while le

• High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture:
  • 76 base instructions
  • Flexible addressing modes
• Two Address Generation Units for Separate Read and Write Addressing of Data Memory
• Special Microcontroller Features:
• Operating Voltage Range of 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
  • 10,000 erase/write
  • 20-year data retention minimum
• Power Management modes:
  • Sleep, Idle, Doze and Alternate Clock modes
  • Operating current 650 µA/MIPS typical at