IS43LQ32128A-062TBLI

IS43LQ32128A-062TBLI is a 128Mb x 32 4Gbit CMOS LPDDR4 SDRAM. The device is organized as 1/2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

• 8 internal banks per channel, ZQ calibration
• LVSTL (low voltage swing terminated logic) I/O interface
• Internal VREF and VREF training, clock-stop capability
• Maximum clock frequency is 1.6GHz (3.2Gbps)
• 16n pre-fetch DDR architecture, programmable burst lengths (16 or 32)
• Single data rate (multiple cycles) command/address bus
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• On-chip temperature sensor whose status can be read from MR4
• 200 ball FBGA package
• Industrial temperature range from -40°C to +95°C