CY7C1061G30-10ZSXIT

CY7C1061G30-10ZSXIT is a CY7C1061G 16Mbit (1M words × 16bit) static RAM with error-correcting code (ECC). To access device with a single chip enable input, assert the chip enable active-low (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs active-low CE1 as LOW and CE2 as HIGH. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected active-low (CE HIGH for a single chip enable device and active-low CE1 HIGH / CE2 LOW for a dual chip enable device), or control signals are de-asserted active-low (OE, BLE, BHE).

• Embedded error-correcting code (ECC) for single-bit error correction
• Low active and standby currents are ICC = 90mA typical at 100MHz, ISB2 = 20mA typical
• 1.0V data retention
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Error indication (ERR) pin to indicate 1-bit error detection and correction
• 10ns speed, 2.2V–3.6V voltage range
• 54-pin TSOP II package
• Dual chip enable
• Industrial ambient temperature range from –40°C to +85°C
• 110mA maximum operating current ICC