PI7C9X2G308GPANJE

PCISIG PCI Express 2.1 certificated Integrated 100MHz Clock buffer for each downstream port Reliability, Availability and Serviceability o Supports Data Poisoning and End-to-End CRC o Advanced Error Reporting and Logging Device State Power Management o Supports D0, D3Hot and D3Cold device power states Advanced Power Savings o Empty downstream ports are set to idle Programmable driver current and de-emphasis level at each individual port Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Extended Virtual Channel capability o Two Virtual Channels (VC) and Eight Traffic Class (TC) support o Independent TC/VC mapping for each port Supports Isochronous Traffic o Isochronous traffic class mapped to VC1 only Supports “Cut-through”(Default) as well as “Store and Forward” mode for switching packets Peer-to-peer switching between any two downstream ports Supports up to 512-byte maximum payload size Power Dissipation: 1.3 W typical in L0 normal mode (Including cloc