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Proven SOM based on the UltraScale+ MPSoC

UltraZed-EV Board Family

UltraZed-EV Board Family

UltraZed-EV

UltraZed-EV™ SOM is a high performance, full-featured, System-On-Module (SOM) based on the AMD Xilinx Zynq® UltraScale+™ MPSoC EV family of devices. Designed in a small form factor, the UltraZed-EV SOM on-board dual system memory, high-speed transceivers, Ethernet, USB, and configuration memory provides an ideal platform for embedded video processing systems. The UltraZed-EV provides easy access to 152 user I/O pins, 26 PS MIO pins, 4 highspeed PS GTR transceivers along with 4 GTR reference clock inputs, and 16 PL high-speed GTH transceivers along with 8 GTH reference clock inputs through three I/O connectors on the backside of the module.

Designers can simply design their own carrier card, plug-in UltraZed-EV SOM, and start their application development with a proven Zynq UltraScale+MPSoC sub-system. Available with the Zynq UltraScale+ MPSoC XCZU7EV-FBVB900 device, the UltraZed-EV SOM enables designers to build multimedia, automotive ADAS, surveillance, and other embedded vision applications with confidence and ease. The MPSoC EV device with its integrated H.264 / H.265 video codec unit is capable of simultaneous encode and decode up to 4Kx2K (60fps).

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UltraZed-EV Features

  • AMD Xilinx XCZU7EV-1FBVB900 device (SOM also supports 4EV, 5EV, 4EG, 5EG, or 7EG device in the FBVB900 package)
  • PS DDR4 SDRAM (4GB, in x64 configuration)
  • PL DDR4 SDRAM (1GB, in x16 configuration)
  • 300 MHz LVDS system clock
  • Dual QSPI Flash (64MB)
  • I2C EEPROM (2Kb)
  • eMMC Flash (8GB, x8)
  • USB 2.0 ULPI PHY
  • Gigabit Ethernet PHY
  • I2C 8-bit I/O expander
  • 2-channel I2C switch/mux
  • PS reference clock input
  • On-board voltage regulators
  • Power-On Reset (POR) circuit
  • Small 4-position boot mode DIP switch
  • 3 JX connectors, providing the following:
    • 152 user PL I/O pins
    • 26 user PS MIO pins (one full MIO bank)
    • 4 PS GTR transceivers (support SATA 3.0, USB 3.0, PCIe Gen2, and DisplayPort interfaces)
    • 4 PS GTR reference clock inputs
    • 16 PL GTH transceivers
    • 8 PL GTH reference clock inputs
    • PS JTAG interface
    • PL SYSMON interface
    • USB 2.0 connector interface
    • Gigabit Ethernet RJ45 connector interface
    • PMBus interface
    • SOM PS VBATT battery input
    • Carrier Card I2C interface
    • SOM Reset input
    • Carrier Card Reset output
    • Carrier Card interrupt input
    • Power Good output, input voltages, and output sense pins
 

Target Applications

  • Embedded system-on-module (SOM)
  • Embedded vision
  • Test & measurement
  • Industrial automation

UltraZed-EV Board Family

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AES-ZU3EG-1-SOM-G

Avnet Engineering Services

UltraZed-EG SOM, Commercial Grade

Datasheet Datasheet

Price USD: $499.0

In Stock: 0

Component Image

AES-ZU3EG-1-SOM-I-G

Avnet Engineering Services

UltraZed-EG SOM, Industrial Grade

Datasheet Datasheet

Price USD: $599.0

In Stock: 0

UltraZed-EV Board Family

Out of Box Designs
SDSoC Baremetal Platform - Xilinx Matrix Multiply Example
SDSoC PetaLinux Platform - Xilinx Matrix Multiply Example
UltraZed-EV Master User Constraint List
UltraZed-EV Ethernet Performance Test Tutorial
UltraZed-EV SATA Performance Test Tutorial
PetaLinux Board Support Packages
Vitis PetaLinux Platform
Vitis PetaLinux Platform PreBuilt Example
Development Using Ubuntu Desktop Linux

These tutorials provide a means to integrate several different technologies on a single platform. Using the Avnet target boards, we have the power of a ARM Cortex-A9 processors, combined with the unrivaled flexibility of Xilinx programmable logic to implement custom hardware systems. We use a Linux kernel as the foundation operating system running on the processor cores which enables a very large ecosystem of software to be run on our development kits. Virtual machines can provide a very convenient Ubuntu development environment for building the hardware platform and cross-compiling software to target the Processing System.

Vitis-AI Tutorials
Specification Description
SOC OPTIONS
  • XCZU7EV-1FBVB900
  • supports 4/5EV, 4/5/7EG in FBVB900 pkg
MEMORY
  • 4GB DDR4 SDRAM
  • 1 GB PL DDR4 SDRAM
  • 64MB Dual QSPI Flash
  • 2Kb I2C EEPROM
  • 8GB eMMC Flash
CONNECTIVITY
  • Uses Carrier Card to break out USB2.0/3.0
  • Tri-Ethernet
  • SATA 3.0, PCIe Gen2/3
  • DisplayPort (see Other)
EXPANSION
  • 200 pin ULTRA-HIGH DENSITY (x2)
  • 120 pin ULTRA-HIGH DENSITY (x1)
VIDEO DISPLAY
  • DisplayPort (Hard IP)
  • Many other protocols supported (Soft IP)
USER INPUTS
  • 152 user PL I/O pins
  • 26 user PS MIO pins (one full MIO bank)
AUDIO
  • HDMI, SDI, and more supported with Carrier
ANALOG
  • Many with supported hardware
  • JTAG and SYSMON supported
POWER
  • 12V (with supported Carrier Card)
CERTIFICATION
  • EMI Radiation Certificate
DIMENSIONS
  • 2.5"x4.0" (height varies depending on thermal solution
CONFIGURATION MEMORY
  • 8GB eMMC Flash
ETHERNET
  • Onboard Tri-Ethernet Hard IP
  • Soft IP capable of 10G Ethernet and Industrial Protocols
GPIO
  • See User Inputs
INTERFACE STANDARDS
  • With Programmable Logic, MPSoC supports nearly all standards
PCIE
  • With supported carrier, PCIe x4 Gen2 or PCIex16 Gen 3
USB
  • USB 2.0/3.0
COMMUNICATIONS
  • USB 2.0/3.0
  • Gigabit Ethernet PHY
  • DisplayPort
  • HDMI
  • SDI
USER I/O
  • See User Inputs
SOFTWARE
  • Fully Supported PetaLinux Operating System with additional capability to work with Vitis and Vitis AI
  • Baremetal and Additional Support for other RTOS as needed or through support partners
OTHER
  • Example Carrier Board supporting
  • DisplayPort, Tri Ethernet, 3G-SDI, HDMI, SATA
  • FPGA Mezzanine Expansion Header, SMA (clocking)
  • PMOD (both PSx1 and PLx2), SFP+ (x2), LVDS (Display), SDCARD

When working with FPGA, before we put the design on hardware we need to be able to verify it lets take a look at how we can do this.

Lets take a look at developing complex FPGA based Hardware based around a model based approach and SoM

This guide provides detailed instructions for targeting the Xilinx Vitis-AI 2.0 flow for Avnet Vitis 2021.2 platforms.

This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.4 flow for Avnet Vitis 2021.1 platforms.

Vitis-AI provides a zoo of pre-built models. This project describes how to leverage these models to implement license plate recognition.

Learn how to add an FFT accelerator for Xilinx MPSoC devices using the Vitis acceleration flow.

This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow for Avnet Vitis 2020.2 platforms.

This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.2 flow for Avnet Vitis 2020.1 platforms.

This guide provides detailed instructions for targeting the VART samples from the Xilinx Vitis-AI 1.1 flow for Avnet Vitis 2019.2 platforms

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UltraZed-EV Board Family

UltraZed-EV Board Family

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UltraZed-EV SOM (for production)

UltraZed-EV Board Family

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