The 'ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable ( OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable ( CEAB\) input must be low to enter data from A or to output data from B. If CEAB\is low andLEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\puts the A latches in the storage mode. With CEAB\and OEAB\both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\inputs.
To ensure the high-impedance state during power up or power down, OEshould be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16543 is characterized for operation from -40°C to 85°C.
Members of the Texas Instruments WidebusTM Family
State-of-the-Art EPIC-IIBTM BiCMOS DesignSignificantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V atVCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration MinimizesHigh-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA IOH, 64-mAIOL)
Package Options Include Plastic 300-mil Shrink Small-Outline(DL) and Thin Shrink Small-Outline (DGG) Packages and 380-milFine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-CenterSpacings