The LP2996-N linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996-N also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Suspend to Ram (STR) Functionality
Low External Component Count
Available in SOIC-8, SO PowerPAD-8 or WQFN-16 packages