STM32F051R8T6

The STM32F051x microcontrollers incorporate the high-performance ARM Cortex-M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 64 Kbytes of Flash memory and 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I²Cs, two SPIs, one I²S, one HDMI CEC and up to two USARTs), one 12-bit ADC, one 12-bit DAC, up to six general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer.The STM32F051x microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.The STM32F051x microcontrollers include devices in six different packages ranging from 32 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F051x peripherals proposed.These features make the STM32F051x microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

• Microcontroller with ARM® 32bit Cortexâ„¢-M0 CPU, frequency up to 48MHz in 64 pin LQFP package
• CRC calculation unit, 64Kb flash, 8KB SRAM
• 2V to 3.6V voltage range, power-on/power down reset (POR/PDR)
• 4 to 32MHz crystal oscillator, internal 40KHz RC oscillator
• 55 GPIO, 5-channel DMA controller, 18 capacitive sensing channels
• (16 ext + 3 int) channels 12bit ADC, one 12bit DAC channel, two analogue comparators
• 1 (16bit) advanced control, 5 (16bit), 1 (32bit) general purpose and 1 (16bit) timers
• Calendar RTC with alarm and periodic wakeup from stop/standby
• SPI, I2C, CEC and USART communication interfaces
• Serial wire debug (SWD), 96bit unique ID, HDMI CEC interface, wakeup on header reception