AT32UC3C2512C-A2UT

The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 66 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Using the Secure Access Unit (SAU) together with the MPU provides the required security and integrity. Higher computation capabilities are achievable either using a rich set of DSP instructions orusing the floating-point instructions. The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access. For applications requiring additional memory, an external memory interface is provided on AT32UC3C0 derivatives. The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from memories to memories without processor involvement. The Peripheral Direct Memory Access (PDCA) controller enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end custumers, who are able to program their own code into the device, accessing the secure libraries, without any risk of compromising the proprietary secure code.

• High Performance, Low Power 32-bit AVR® Microcontroller
  • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
  • Built-in Floating-Point Processing Unit (FPU)
  • Read-Modify-Write Instructions and Atomic Bit Manipulation
  • Performing 1.49 DMIPS / MHz
  • Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
  • Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State)
  • Memory Protection Unit
• Multi-hierarchy Bus System
  • High-Performance Data Transfers on Separate Buses for Increased Performance
  • 16 Peripheral DMA Channels Improves Speed for Peripheral Communication
• Internal High-Speed Flash
  • 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions
  • Single Cycle Access up to 33 MHz
  • FlashVault™ Technology Allows Pre-programmed Secure Library Support for End User Applications
  • Prefetch Buffer Optimizing Instruction Execution at Maximum Speed