PC7410VG450NE

The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the Power Architecture Reduced Instruction Set Computer (RISC) architecture. It is fully JTAG-compliant.

The PC7410 maintains some of the characteristics of G3 microprocessors:•The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units•The microprocessor provides four software controllable power-saving modes and a thermal assist unit management • The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags

In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro- tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec® technology instruction set.

New features have been developed to make latency equal for double-precision and single-precision floating-point opera- tions involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, high- bandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.

• 22.8 SPECint95 (Estimated), 17SPECfp95 at 500 MHz (Estimated)
• 917MIPS at 500 MHz
• Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)
• Seven Selectable Core-to-L2 Frequency Divisors
• Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)
• Selectable L2 interface of 1.8V or 2.5V
• PDTypical 5.3W at 500 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Saving
• Superscalar (Four Instructions Fetched per Clock Cycle)
• 4 GB Direct Addressing Range
• Virtual Memory: 4 hexabytes (252)
• 64-bit Data and 32-bit Address Bus Interface
• 32 KB Instruction and Data Cache
• Eight Independent Execution Units and Three Register Files
• Write-back and Write-through Operations
• fINTMax = 450 MHz 500 MHz
• fBUSMax = 133 MHz