EVX10AS180AGS

The EV10AS180A is a 10-bit 1.5 GSps ADC. The device includes a front-end Track and Hold stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by a DEMUX with 100 Ohm differential output buffers.

The EV10AS180A works in fully differential mode from analog inputs up to digital outputs. It operates in the first Nyquist and L-Band (Fin ranging from DC to 1800 MHz). DEMUX Ratio (1:1 or 1:2 or 1:4) can be selected with the 2 pins RS0, RS1. DEMUX outputs are synchronous on each port.

A differential Data Ready output is available to indicate when the outputs are valid. The Data Ready DR, DRN is common to the 4 ports.

A power up reset ensures to synchronize internal signals and ensures output data to be properly ordered. An external Reset (RSTN) can also be used. The gain control pin GA and offset control OA are provided to adjust the ADC gain and offset transfer function.

The swing of ADC output buffers can be lowered through the SA pin.

• Single Core ADC Architecture with 10-bit Resolution Integrating a Selectable 1:1/2/4 DEMUX
• 1.5 GSps Guaranteed Conversion Rate
• Differential Input Clock (AC Coupled)
• Analog Input Voltage: 500 mVpp Differential Full Scale (AC Coupled)
• Analog and Clock Input Impedance: 100? Differential
• LVDS Differential Output Data with Swing Adjustment and Data Ready
• Fine Adjustment of ADC Gain, Offset
• Fine Adjustment of Sampling Delay for Interleaving
• Static and Dynamic Test Mode for ADC and DEMUX
• Data Ready Common to the 4 Output Ports
• 1.75W Power Dissipation (1:2 Ratio with Standard LVDS Output Swing)
• Power Supply: 5.2V, 3.3V and 2.5V (Output Buffers)
• LGA255, Ci-CGA255 or CCGA255 Package