STM8TL52F4P6TR

The STM8TL52x4 devices feature the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. It uses a ProxSense charge transfer capacitive acquisition method that is capable of near range proximity detection.

Includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming. All STM8TL52x4 microcontrollers feature low-power low-voltage singlesupply program Flash memory.

The STM8TL52x4 devices are based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

• Operating conditions
  • Operating power supply: 1.65 V to 3.6 V
  • Temperature range: - 40°C to 85°C
• Low power:
  • 4 low power modes: Wait, Active-halt with AWU (1 µA), Active-halt with ProxSense™ (10 µA with scan every 200 ms), Halt (0.4 µA)
  • Dynamic power consumption: 150 µA/MHz
  • Fast wakeup from Halt mode: 4.7 µs
  • Ultra-low leakage per I/O: 50 nA
• Advanced STM8 Core
  • Harvard architecture with 3-stage pipeline
  • Max freq.16 MHz,16 CISC MIPS peak
• Memories
  • Up to 16 Kbyte of Flash program including up to 2 Kbyte of data EEPROM
  • Error correction code (ECC)
  • Flexible write and read protection modes
  • In-application and in-circuit programming
  • Data EEPROM capability
  • 4 Kbyte of static RAM
• Clock management
  • Internal 16 MHz factory-trimmed RC
  • Internal 38 kHz low consumption RC driving both the IWDG an