STM32F778AIY6TR

The STM32F778Ax device is based on the high performance ARM Cortex-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex-M7 core features a floating point unit (FPU) which supports ARM doubleprecision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.

The STM32F778Ax device incorporates high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM, 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access.

All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32- bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces.
Up to four I2Cs
Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI)
Three CANs
Two SAI serial audio interfaces
Two SDMMC host interfaces
Ethernet and camera interfaces
LCD-TFT display controller
Chrom-ART Accelerator™
SPDIFRX interface
HDMI-CEC Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors and a cryptographic acceleration cell.

The

• Core: ARM® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
• Memories
  • Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write
  • SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM
  • Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
• Dual mode Quad-SPI
• Graphics
  • Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface
  • Hardware JPEG codec
  • LCD-TFT controller supporting up to XGA resolution
  • MIPI® DSI host controller supporting up to 720p 30