AT45DB081E-SSHNHA-T

The AT45DB081E is a 1.7V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety ofdigital voice, image, program code, and data storage applications. The AT45DB081E also supports the RapidS serialinterface for applications requiring very high speed operation. Its 8,650,752 bits of memory are organized as 4,096 256 bytes or 264 bytes each. In addition to the main memory, the AT45DB081E also contains two SRAM buffers of256/264 bytes each. The buffers allow receiving of data while main memory is being reprogrammed.Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. Inaddition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation (bit or bytealterability) can be easily handled with a self-contained three step read-modify-write operation.Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, theDataFlash uses a serial interface to sequentially access its data. The simple sequential access dramatically reducesactive pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, andreduces package size. The device is optimized for use in many commercial and industrial applications wherehigh-density, low-pin count, low-voltage, and low-power are essential.To allow for simple in-system re-programmability, the AT45DB081E does not require high input voltages forprogramming. The device operates from a single 1.7V to 3.6V power supply for the erase and program and readoperations. The AT45DB081E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consistingof the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).All programming and erase cycles are self-timed.

• Single 1.7V - 3.6V supply
• Serial Peripheral Interface (SPI) compatible
• Supports SPI modes 0 and 3
• Supports RapidS™ operation
• Continuous read capability through entire array
• Up to 85MHz
• Low-power read option up to 15MHz
• Clock-to-output time (tV) of 6ns maximum
• User configurable page size
• 256 bytes per page
• 264 bytes per page (default)
• Page size can be factory pre-configured for 256 bytes
• Two fully independent SRAM data buffers (256/264 bytes)
• Allows receiving data while reprogramming the main memory array
• Flexible programming options
• Byte/Page Program (1 to 256/264 bytes) directly into main memory
• Buffer Write
• Buffer to Main Memory Page Program
• Flexible erase options
• Page Erase (256/264 bytes)
• Block Erase (2KB)
• Sector Erase (64KB)
• Chip Erase (8-Mbits)
• Program and Erase Suspend/Resume
• Adva