8SLVP1204ANLGI/W

8SLVP1204ANLGI/W is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1204 ideal for clock distribution applications that demand well-defined performance and repeatability. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential PCLKx pairs can accept the following differential input levels: LVDS, LVPECL, CML
• 2GHz maximum input clock frequency
• LVCMOS interface levels for the control input, (input select)
• 5ps typical output skew (VCC = 3.3V ± 5% or 2.5V ±5%, VEE = 0V, TA = -40 to 85°C)
• 200ps typical propagation delay (PCKx, nPCLKx to any Qx, nQx for VPP = 0.1V or 0.3V)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12KHz - 20MHz 40fs (maximum), at 3.63V
• Maximum device current consumption (IEE): 60mA (maximum), at 3.63V
• 16-VFQFPN package, ambient operating temperature range from -40°C to +85°C