8P34S1212NLGI8

The IDT8P34S1212I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8P34S1212I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8P34S1212I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK0, CLK1 pairs can accept the following differential input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 10ps (typical)
• Propagation delay: 340ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz- 20MHz: 41fs (typical)
• Maximum device current consumption (IDD): 227mA (maximum) @ 1.89V
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature