82V3391BEQG

The IDT82V3391 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, Stratum 4E, Stratum 4, SMC, EEC-Option1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device supports several types of input clock sources: recovered clock from Synchronous Ethernet, STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH / Synchronous Ethernet network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 path. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. There are 2 high performance APLLs that can be used for low jitter SONET and Ethernet Clocks. The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A highly stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports six microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola, I2C

• Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, Stratum 4E, Stratum 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks
• Supports 1PPS input and output
• Employs PLL architecture to feature excellent jitter performance and minimize the number of external components
• Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or locks to T0 DPLL
• Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Provides OUT1~OUT7 output clocks whose frequency cover from 1PPS to 644.53125 MHz
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