72V2113L7-5BCI

The ID72V2113 is exceptionally deep, high speed, CMOSFirst-In-First-Out (FIFO) memories with clocked read and write controls and aflexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improvementsover previous SuperSync FIFOs, including the following: Flexible x9/x18 Bus-Matching on both read and write ports.• The limitation of the frequency of one clock input with respect to the other hasbeen removed. The Frequency Select pin (FS) has been removed, thus itis no longer necessary to select which of the two clock inputs, RCLK or WCLK,is running at the higher frequency.• The period required by the retransmit operation is now fixed and short.• The first word data latency period, from the time the first word is written to anempty FIFO to the time it can be read, is now fixed and short. (The variableclock cycle counting delay associated with the latency period found onprevious SuperSync devices has been eliminated on this SuperSync family.)• Asynchronous/Synchronous translation on the read or write ports.• High density offerings up to 4 Mbit. Bus-Matching SuperSync FIFOs are particularly appropriate for network,video, telecommunications, data communications and other applications thatneed to buffer large amounts of data and match busses of unequal sizes.

• IDT72V2113 ? 262,144 x 18/524,288 x 9
• Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (BGA Only)
• 6 ns read/write cycle time (4.0 ns access time)
• User selectable input and output port bus-sizing
  • x9 in to x9 out
  • x9 in to x18 out
  • x18 in to x9 out
  • x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V tolerant inputs
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
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