71V35761S166PFGI

The IDT71V35761 are high-speed SRAMs organized as 128K x 36. The IDT71V35761 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V35761 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V35761 SRAMs utilize a high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and 165 fine pitch ball grid array(fBGA).

• 128K x 36 memory configuration
• Supports high system speed:
  • Commercial: - 200MHz 3.1ns clock access time
  • Commercial and Industrial: - 183MHz 3.3ns clock access time - 166MHz 3.5ns clock access time
• LBO input selects interleaved or linear burst mode
• 3.3V core power supply
• Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
• Power down controlled by ZZ input
• 3.3V I/O
• Optional - Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
• Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array