NLV74HC74ADR2G
Flip Flop, 74HC74, D, 17 ns, 35 MHz, 5.2 mA, 14 Pins, NSOIC
-
RoHS 10 Compliant -
Tariff Charges
The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous.
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 128 FETs or 32 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free and are RoHS Compliant
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| HC | ||
| D-Type | ||
| 260 | ||
| -5.2 mA | ||
| 105@2V|80@3V|21@4.5|18@6V ns | ||
| 0.002 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 2 | ||
| 1 | ||
| 1 | ||
| 2 | ||
| 0 | ||
| -55 to 125 °C | ||
| Differential | ||
| 14SOIC | ||
| 14 | ||
| Inverting|Non-Inverting | ||
| 8.75(Max) x 4(Max) x 1.5(Max) | ||
| 50 pF | ||
| No | ||
| Automotive | ||
| Set, Reset | ||
| SOIC | ||
| Positive-Edge | ||
| 2.5|3.3|5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542330001 |
| Schedule B: | 8542330000 |
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