NLV74HC573ADWR2G
Octal 3-State Non-inverting Transparent Latch
The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HCT373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.
- Output Drive Capability: 15 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- Chip Complexity: 218 FETs or 54.5 Equivalent Gates
- These Devices are Pb-Free and are RoHS Compliant
- NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q1100 Qualified and PPAP Capable
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Transparent | ||
| Matte Tin | ||
| HC | ||
| 260 | ||
| -7.8 mA | ||
| 7.8 mA | ||
| 150@2V|100@3V|30@4.5V|26@6V ns | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 8 | ||
| 1 | ||
| 1 | ||
| 8 | ||
| 1 | ||
| 8 | ||
| 0 | ||
| -55 to 125 °C | ||
| 3-State | ||
| 20SOIC W | ||
| 20 | ||
| Non-Inverting | ||
| 12.95(Max) x 7.6(Max) x 2.4(Max) | ||
| 50 pF | ||
| No | ||
| Automotive | ||
| No | ||
| SOIC | ||
| D-Type |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542330001 |
| Schedule B: | 8542330000 |
Factory Lead Time: