NB7V32MMNG
Clock Buffer, Divider, 10 GHz to 1 Output, 1.71 V to 2.625 V, 16 Pins, QFN-EP
- RoHS 10 Compliant
- Tariff Charges
The NB7V32M is a differential divide-by-2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a divide-by-2 output copy of an input Clock operating up to 10GHz with minimal jitter. The Reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M's in a system. The 16mA differential CML output provides matching internal 50-ohm termination which guarantees 400mV output swing when externally receiver terminated with 50-ohm to VCC. The NB7V32M is the 1.8V/2.5V version of the NB7L32M 2.5V/3.3V and is offered in a low profile 3mm x 3mm 16-pin QFN package.
- Maximum Input Clock Frequency > 10 GHz, typical
- Random Clock Jitter < 0.8ps RMS
- 30ps Typical Rise and Fall Times
- Differential CML Outputs, 400mV peak-to-peak, typical
- -40°C to +85°C Ambient Operating Temperature
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Clock Divider | ||
| QFN-EP | ||
| >10000 MHz | ||
| 10 GHz | ||
| CML, LVCMOS, LVDS, LVPECL | ||
| 1 | ||
| 1 | ||
| 16 | ||
| 85 °C | ||
| -40 °C | ||
| CML | ||
| NB7V32M Series | ||
| 2.625 Vdc | ||
| 1.71 Vdc |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |