NB3L83948CFAG

The NB3L83948C is a pure 2.5 / 3.3 V (VDD = VDDO) or mixed mode 3.3 Core / 2.5 V Output (VDDO) clock distribution buffer with the capability to select either a differential LVPECL / LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL compatible input clock, such as a Primary and a Test Clock. All other control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS level compatible.

• 2.5 V / 3.3V (VDD = VDDO) or
  3.3 VDD / 2.5 VCCO Operation
• 350 MHz clock support
• LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS Clock Capability
• LVCMOS Compatible Control Inputs
• 12 Clock Outputs
• Synchronous Clock Select
• Output Enable to High Z State Control
• 100 ps Max. Skew Between Outputs
• Industrial Temp. Range
• 32pin TQFP Package
• These are PbFree Devices