MM74HCT373WM
3-STATE Octal D-Type Latch
The MM74HCT373 octal D-type latches advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The 3-STATE outputs are capable of driving 15 LSTTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT373 LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
- TTL input characteristic compatible
- Typical propagation delay: 20 ns
- Low input current: 1 PA maximum
- Low quiescent current: 80 PA maximum
- Compatible with bus-oriented systems
- Output drive capability: 15 LS-TTL loads
Technical Attributes
Find Similar Parts
Description | Value | |
---|---|---|
No | ||
Transparent | ||
Matte Tin | ||
HCT | ||
260 | ||
-7.2 mA | ||
7.2 mA | ||
40@5V ns | ||
Surface Mount | ||
MSL 1 - Unlimited | ||
8 | ||
1 | ||
1 | ||
8 | ||
1 | ||
8 | ||
0 | ||
-40 to 85 °C | ||
3-State | ||
20SOIC W | ||
20 | ||
Non-Inverting | ||
13 x 7.6 x 2.35 mm | ||
150 pF | ||
No | ||
No | ||
SOIC W | ||
D-Type |
ECCN / UNSPSC / COO
Description | Value |
---|---|
Country of Origin: | RECOVERY FEE |
ECCN: | EAR99 |
HTSN: | 8542390050 |
Schedule B: | 8542390060 |