MM74HC175MX
Flip-Flop, Complementary Output, Positive Edge, 74HC175, D, 15 ns, 70 MHz, NSOIC
- RoHS 10 Compliant
- Tariff Charges
The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Information at the D inputs of the MM74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available. All four flip-flops are controlled by a common clock and a common CLEAR. Clearing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are cleared to a logical “0” and all four Q outputs to a logical “1.”. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
- Typical propagation delay: 15 ns
- Wide operating supply voltage range: 2–6V
- Low input current: 1 µA maximum
- Low quiescent supply current: 80 µA maximum (74HC)
- High output drive current: 4 mA minimum (74HC)
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| HC | ||
| D-Type Bus Interface | ||
| 260 | ||
| -5.2 mA | ||
| 150@2V|30@4.5V|26@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 4 | ||
| 4 | ||
| 4 | ||
| 1 | ||
| 0 | ||
| -40 to 85 °C | ||
| Differential | ||
| 16SOIC N | ||
| 16 | ||
| Inverting|Non-Inverting | ||
| 10 x 4 x 1.5 mm | ||
| 50 pF | ||
| No | ||
| Master Reset | ||
| SOIC N | ||
| Positive-Edge | ||
| 2.5|3.3|5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |