MC74HC175ADR2G
Quad D Flip-Flop with Common Clock and Reset. ONSSPCLGC;
- RoHS 10 Compliant
- Tariff Charges
High-Performance Silicon-Gate CMOSThe MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D inputis transferred to the corresponding Q output on the next positive going edge of the Clock input.
- Output Drive Capability: 10 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2 to 6 V
- Low Input Current: 1 mA
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- Chip Complexity 166 FETs or 41.5 Equivalent Gates
- Pb-Free Packages are Available*
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| HC | ||
| D-Type Bus Interface | ||
| 260 | ||
| -5.2 mA | ||
| 150@2V|75@3V|26@4.5V|22@6V ns | ||
| 0.004 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 4 | ||
| 4 | ||
| 4 | ||
| 1 | ||
| 0 | ||
| -55 to 125 °C | ||
| Differential | ||
| 16SOIC | ||
| 16 | ||
| Inverting|Non-Inverting | ||
| 10 x 4 x 1.5 mm | ||
| 50 pF | ||
| No | ||
| Master Reset | ||
| SOIC | ||
| Positive-Edge | ||
| 2.5|3.3|5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |