MC14099BDWR2G
8-Bit Addressable Latch. ONSSPCLGC;
The MC14099B and MC14599B are 8-bit addressable latches. Data is entered in serial form when the appropriate latch is addressed (via address pins A0, A1, A2) and write disable is in the low state. Chip enable must be high for writing into MC14599B. For the MC14599B the data pin is a bidirectional data port and for the MC14099B the input is a unidirectional write only port. The Write/Read line controls this port in the MC14599B. The data is presented in parallel at the output of the eight latches independently of the state of Write Disable, Write/Read or Chip Enable. A Master Reset capability is available on both parts.
- Serial Data Input
- Parallel Output
- Master Reset
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load over the Rated Temperature Range
- MC14099B pin for pin compatible with CD4099B
- Pb-Free Packages are Available*
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Addressable | ||
| Matte Tin | ||
| 4000 | ||
| 260 | ||
| 400@5V|150@10V|100@15V ns | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 8 | ||
| 1 | ||
| 1 | ||
| 1 | ||
| 0 | ||
| 8 | ||
| 3 | ||
| -55 to 125 °C | ||
| 16SOIC W | ||
| 16 | ||
| Non-Inverting | ||
| 10.45 x 7.6 x 2.4 mm | ||
| 50 pF | ||
| No | ||
| Master Reset | ||
| SOIC W | ||
| D-Type |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390070 |
| Schedule B: | 8542390060 |
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