MC14044BDR2G
Latch, MC14044, SR, Tri State, 175 ns, SOIC
The MC14044BDR2G is a quad R-S Latch constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical 1 or high on the enable input, a logical 0 or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. The outputs are capable of driving two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
- Double diode input protection
- Three-state outputs with common enable
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Transparent | ||
| Matte Tin | ||
| 4000 | ||
| 260 | ||
| -4.2(Min) mA | ||
| 4.2(Min) mA | ||
| 350@5V|175@10V|120@15V ns | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 4 | ||
| 1 | ||
| 0 | ||
| 8 | ||
| 1 | ||
| 4 | ||
| 0 | ||
| -55 to 125 °C | ||
| 3-State | ||
| 16SOIC | ||
| 16 | ||
| Non-Inverting | ||
| 10 x 4 x 1.5 mm | ||
| 50 pF | ||
| No | ||
| No | ||
| SOIC | ||
| SR-Type |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
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