MC14027BDR2G
Flip-Flop, MC14027B, JK, 75 ns, 13 MHz, SOIC
- RoHS 10 Compliant
- Tariff Charges
The MC14027B dual JK flip-flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.
- Diode Protection on All Inputs
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Swing Independent of Fanout
- Logic Edge-Clocked Flip-Flop Design:Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive-going edgeof the clock pulse
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pin-for-Pin Replacement for CD4027B
- Pb-Free Packages are Available*
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| 4000 | ||
| JK-Type | ||
| 260 | ||
| -4.2 mA | ||
| 350@5V|150@10V|100@15V ns | ||
| 0.004 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 2 | ||
| 2 | ||
| 1 | ||
| 2 | ||
| 0 | ||
| -55 to 125 °C | ||
| Differential | ||
| 16SOIC | ||
| 16 | ||
| Inverting|Non-Inverting | ||
| 10 x 4 x 1.5 mm | ||
| 50 pF | ||
| No | ||
| Set, Reset | ||
| SOIC | ||
| Positive-Edge | ||
| 3.3|5|9|12|15 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |