MC14018BDR2G
Divide-By-N Counter, 8 MHz, 3 V to 18 V, SOIC-16
The MC14018B contains five Johnson counter stages which are asynchronously presettable and resettable. The counters are synchronous, and increment on the positive going edge of the clock. Presetting is accomplished by a logic 1 on the preset enable input. Data on the Jam inputs will then be transferred to their respective Qbar outputs (inverted). A logic 1 on the reset input will cause all Qbar outputs to go to a logic 1 state. Division by any number from 2 to 10 can be accomplished by connecting appropriate Qbar outputs to the data input. Anti-lock gating is included in the MC14018B to assure proper counting sequence.
- Fully Static Operation
- Schmitt Trigger on Clock Input
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pin-for-Pin Replacement for CD4018B
- Pb-Free Packages are Available*
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Matte Tin | ||
| 4000 | ||
| Counter/Divider | ||
| 260 | ||
| 620@5V|240@10V|170@15V ns | ||
| 0.02 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 5 | ||
| 1 | ||
| 0 | ||
| 5 | ||
| -55 to 125 °C | ||
| UP Counter | ||
| 16SOIC | ||
| No | ||
| 16 | ||
| Asynchronous | ||
| 10 x 4 x 1.5 mm | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| SOIC | ||
| No | ||
| Positive-Edge | ||
| Binary | ||
| 3.3|5|9|12|15 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
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