MC10EP33DR2G

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.The V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage.V may also rebias AC coupled inputs. When used, decouple V and V via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.The 100 Series contains temperature compensation.

• 320ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: V_CC= 3.0 V to 5.5 V with V_EE= 0 V
• NECL Mode Operating Range: V_CC= 0 V with V_EE= -3.0 V to -5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output will default LOW with inputs open or at V_EE
• V_BB Output
• Pb-Free Packages are Available