MC100LVEL32DG
3.3 V ECL ÷2 Divider
- RoHS 10 Compliant
- Tariff Charges
The MC100LVEL32 is an integrated w2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple LVEL32's in a system.The V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V and V via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V should be left open.
- 510ps Propagation Delay
- 2.6 GHz Typical Maximum Frequency
- ESD Protection: >4 KV HBM, >200 V MM
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
- NECL Mode Operating Range: VCC= 0 V with VEE = -3.0 V to -3.8 V
- Internal Input Pulldown Resistors
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D - Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
- Transistor Count = 111 devices
- Pb-Free Packages are Available
Technical Attributes
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Description | Value | |
---|---|---|
Divider | ||
Matte Tin | ||
ECL | ||
265 | ||
Surface Mount | ||
MSL 1 - Unlimited | ||
1 | ||
1 | ||
2 V | ||
-40 to 85 °C | ||
8SOIC N | ||
8 | ||
5 x 4 x 1.5 mm | ||
No | ||
SOIC N |
ECCN / UNSPSC / COO
Description | Value |
---|---|
Country of Origin: | RECOVERY FEE |
ECCN: | EAR99 |
HTSN: | 8542390050 |
Schedule B: | 8542390060 |