MC100EPT23DG
Translator, 2 Inputs, 50mA, 1.5ns, 3V to 3.6V, SOIC-8
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RoHS 10 Compliant -
Tariff Charges
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external V reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a V of +3.3V.
- 1.5ns Typical Propagation Delay
- Maximum Operating Frequency > 275MHz
- 24mA LVTTL Outputs
- Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V
- Open Input Default State
- Q Output will default LOW with inputs open or at GND
- Pb-Free Packages are Available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Matte Tin | ||
| ECL | ||
| Translator | ||
| 265 | ||
| -3 mA | ||
| 24 mA | ||
| 1.8@3V to 3.6V ns | ||
| 40 mA | ||
| Surface Mount | ||
| 1 | ||
| 3 to 3.6 V | ||
| -40 to 85 °C | ||
| 8NSOIC | ||
| 8 | ||
| 5 x 4 x 1.5 mm | ||
| No | ||
| Industrial | ||
| NSOIC | ||
| CML/LVDS/LVPECL to LVCMOS/LVTTL |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
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