MC100EP91DWG

The MC100EP91DWG is a triple any level positive input to NECL Output Translator accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals and translates them to differential NECL output signals (-3/-5.5V). To accomplish the level translation the EP91 requires three power rails. The VCC pins should be connected to the positive power supply and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors. Under open input conditions, the D\ input will be biased at VCC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state and Q outputs to a high state, which will ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs.

• Maximum input data rate 2Gb/s typical
• Q Output will default low with inputs open or at GND
• 2GHz Typical maximum input clock frequency