MC100EP51DG
Flip-Flop, with Reset and Differential Clock, Differential, ECL, Positive Edge, D, 370 ps, 3 GHz
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Manufacturer:onsemi
Product Category:
Logic ICs, Flip Flops
Avnet Manufacturer Part #: MC100EP51DG
Secondary Manufacturer Part#: MC100EP51DG
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RoHS 10 Compliant -
Tariff Charges
The MC100EP51DG is a differential clock D-type Flip-flop with reset. It is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK\ input will be biased at VCC/2. The 100 series contains temperature compensation.
- Open input default state
- Safety clamp on inputs
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| ECL | ||
| 265 | ||
| -50 mA | ||
| 0.45@3V to 5.5V ns | ||
| -3, 3 V | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 1 | ||
| 1 | ||
| 1 | ||
| 1 | ||
| 0 | ||
| -40 to 85 °C | ||
| Differential | ||
| 8SOIC N | ||
| 8 | ||
| Inverting|Non-Inverting | ||
| 5 x 4 x 1.5 mm | ||
| No | ||
| Reset | ||
| SOIC N | ||
| Positive-Edge/Negative-Edge | ||
| -3.3|-5|3.3|5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: