MC100EP446FAG

The MC100EP446FAG is a 8-bit parallel to serial Data Converter designed with unique circuit topology to operate for NRZ data rates up to 3.2Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal clock data rate using the CKSEL pin. Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, VBB pin is provided for single-ended input condition. The 100 series device contains temperature compensation network.

• Differential clock and serial outputs
• VBB Output for single-ended input applications
• Asynchronous data reset (SYNC)
• Open input default state
• Safety clamp on inputs
• Parallel interface can support PECL, TTL or CMOS
• 3.2Gbps Typical data rate capability