MC100EP40DTG

The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply.When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.When Reference (R) and Feedback (FB) inputs are 80 pSor less in phase difference, the Phase Lock Detect pin will indicate lock by a high state. The V (V, Vbar , V , Vbar ) pins offer an internal termination network for 50 line impedance environment. An external sinking supply of V-2 V is required on V pin(s). If you short the two differential V and V (or V and Vbar ) together, you provide a 100 termination resistance that is compatible with LVDS signal receiver termination. The V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V and V via a 0.01 F capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, V should be left open. Special considerations are required for differential inputs under No Signal conditio.

• Maximum Frequency > 2 Ghz Typical
• Fully Differential
• Advanced High Band Output Swing of 400 mV
• Theoretical Gain = 1.11
• T_rise 97 pS Typical, F_fall 70 pS Typical
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V to -5.5 V
• 50O Internal Termination Resistor
• These are Pb-Free Devices