MC100EP35DTG
ECL JK Flip-Flop
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Manufacturer:onsemi
Product Category:
Logic ICs, Flip Flops
Avnet Manufacturer Part #: MC100EP35DTG
Secondary Manufacturer Part#: MC100EP35DTG
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RoHS 10 Compliant -
Tariff Charges
The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.The 100 Series contains temperature compensation.
- 410 ps Propagation Delay
- Maximum Frequency > 3 GHz Typical
- PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range:VCC = 0 V with VEE = -3.0V to -5.5V
- Open Input Default State
- Q Output will default LOW with inputs open or at VEE
- Pb-Free Packages are Available
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Matte Tin | ||
| ECL | ||
| JK-Type | ||
| 265 | ||
| -50 mA | ||
| 0.49@3V to 5.5V ns | ||
| -3, 3 V | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 1 | ||
| 2 | ||
| 1 | ||
| 1 | ||
| 0 | ||
| -40 to 85 °C | ||
| Differential | ||
| 8TSSOP | ||
| 8 | ||
| Inverting|Non-Inverting | ||
| 3.1 x 3.1 x 0.95 mm | ||
| No | ||
| Reset | ||
| TSSOP | ||
| Positive-Edge | ||
| -3.3|-5|3.3|5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: