SPC5748GGK1MMJ6

SPC5748GGK1MMJ6 is a microcontroller featuring 2 x 160MHz Power Architecture® e200Z4 dual issue, 32bit CPU and 1 x 80MHz Power Architecture® e200Z2 single issue 32bit CPU, end to end ECC, clock interfaces such as 8-40MHz external crystal (FXOSC), 16MHz IRC (FIRC), 128KHz IRC (SIRC), 32KHz external crystal (SXOSC, clock monitor unit (CMU), frequency modulated phase-locked loop (FMPLL) and Real Time Counter (RTC), 2x System Memory Protection Unit (SMPU) each with 16 region descriptors and 16-byte region granularity, 16 Semaphores to manage access to shared resource, Interrupt controller (INTC) capable of routing interrupts to any CPU, multiple crossbar switch architecture for concurrent access to peripherals, flash, and RAM from multiple bus, Boot Assist Flash (BAF) supports internal flash programming via a serial link (LIN / SCI). Configurable I/O domains supporting FLEXCAN, LINFlex, Ethernet, USB, MLB, uSDHC and general I/O.

• Automotive qualified and power architecture in 55nm
• e200z4 Core version and 6MB flash memory size, 6MB flash memory size
• Gateway feature set and CAN FD, 2nd Ethernet option and TSMC fab
• Supports wake-up from low power modes via the WKPU controller
• On-chip voltage regulator (VREG)
• DSPI, SPI, LIN, four inter-IC communication interface (IIC), 2 x ENET with L2 switch
• 3 x Synchronous Audio Interface (SAI), on-chip voltage regulator (VREG)
• 16 periodic interrupt timers, three system timer module and four software watchdog timers (SWT)
• ISO26262 ASIL compliance functional safety and includes enhanced low power operation
• 256 pin MAPBGA package