SPC5673KAVMM1R

MPC5500/5600 family, it contains the Book E compliant Power Architecture? technology core with Variable Length Encoding (VLE). This core complies with the Power Architecture embedded category, and is 100 percent user mode compatible with the original Power PC user instruction set architecture (UISA). It offers system performance up to four times that of its MPC5561 predecessor, while bringing you the reliability and familiarity of the proven Power Architecture technology. A comprehensive suite of hardware and software development tools is available to help simplify and speed system design. Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments.

• High-performance e200z7d dual core
• Memory available
• SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection
• Decoupled Parallel mode for high-performance use of replicated cores
• Nexus Class 3+ interface
• Interrupts
• GPIOs individually programmable as input, output, or special function
• 3 general-purpose eTimer units (6 channels each)
• 3 FlexPWM units with four 16-bit channels per module
• Communications interfaces
• Four 12-bit analog-to-digital converters (ADCs)
• External bus interface
• 16-bit external DDR memory controller
• Parallel digital interface (PDI)
• On-chip CAN/UART bootstrap loader
• Capable of operating on a single 3.3 V voltage supply
• Operating junction temperature range –40 to 150 °C