SPC5554MVR132

The Freescale MPC5554 MCU enables complex, real-time control for engine management systems. It offers system performance of up to five times that of its MPC500 predecessors along with the reliability and familiarity of proven Power Architecture technology. Reduces costs by integrating more functionality on-chip Development support speeds time-to-market Supports multiple protocols and customer requirements through intelligent subsystems Offers a migration path from the MPC500 MCUs, facilitating reuse of legacy software architectures

Freescale's e200z6 Core

• High-performance 132 MHz 32-bit core built on Power Architecture technology
• Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
• SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

• 2 MB of embedded flash memory with error correction coding (ECC) and read while write (RWW) capability
• 64 KB on-chip static RAM with ECC
• 32 KB of cache (with line-locking) that can be configured as additional RAM

System

• Two enhanced time processor units (eTPUs) with 64 I/O channels and 19 KB of designated SRAM
• 64-channel enhanced direct memory access (eDMA) controller
• Interrupt controller (INTC) capable of handling 286 selectable-priority interrupt sources
• Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
• MPC500 compatible external