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S9S08SG32E1MTL

8 Bit MCU, S08 Family S08SG Series Microcontrollers, HCS08, 40 MHz, 32 KB, 28 Pins, TSSOP

Official logo for NXP
Manufacturer:NXP
Avnet Manufacturer Part #: S9S08SG32E1MTL
Secondary Manufacturer Part#: S9S08SG32E1MTL
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

Freescale’s 8-bit S08SG family of microcontrollers (MCUs) is an entry-level to mid-range offering designed for LIN slave, general market, high-temperature (up to 150 °C ambient) and space-constrained applications. The SG is easy to design into an application because of its non-intrusive, single-wire background debug module (BDM), which allows you to read registers without stopping execution on the chip. This reduces development time, since changes can be made while in application and in real time. It also allows debug access in constrained locations. The SG helps to lower cost, save board space and improve quality with on-chip components by eliminating the need for external crystal, low-voltage interrupt (LVI) circuit, voltage regulator, I/O mux, watchdog circuit, analog-to-digital converter (ADC) and development tools. The SG family is also pin-compatible with the S08EL and S08SL families. This flexibility allows for upgrading and downgrading without major board redesign or long and expensive development times.

  • 40 MHz core
  • 4-32 KB flash range
  • 256B-1 KB RAM range
  • 1 universal asynchronous receiver/transmitter (UART), 1 serial peripheral interface (SPI), 1 inter-integrated circuit (IIC)
  • Up to 16-channel, 10-bit ADC
  • 1 analog comparator
  • In-circuit emulation (ICE) with real-time bus capture
  • Single-wire background debug module (BDM)
  • Four package options
  • Technical Attributes

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    Description Value
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    40
    125 °C
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    AEC-Q100

    ECCN / UNSPSC / COO

    Description Value
    Country of Origin: NO RECOVERY FEE
    ECCN: EAR99
    HTSN: 8542310015
    Schedule B: 8542310075
    In Stock :  0
    Additional inventory
    Factory Lead Time: 112 Weeks
    Price for: Each
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