PTN3360DBS,518

The PTN3360D is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit deep color mode, 4K × 2K video format or 3D video data transport. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 O to 3.3 V on the sink side. Additionally, the PTN3360D provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using active I²C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3360D typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.4b specification. By using PTN3360D, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. The PTN3360D main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steerin

• High-speed TMDS level shifting
  • Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals
  • TMDS level shifting operation up to 3.0 Gbit/s per lane (300 MHz character clock) supporting 4K ? 2K and 3D video formats
  • Programmable equalizer
  • Integrated 50 ? termination resistors for self-biasing differential inputs
  • Back-current safe outputs to disallow current when device power is off and monitor is on
  • Disable feature to turn off TMDS inputs and outputs and to enter low-power state
• DDC level shifting
  • Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
  • Rise time accelerator on sink-side DDC ports
  • 0 Hz to 400 kHz I2C-bus clock frequency
  • Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled