PCA9641PWJ

The PCA9641 is a 2-to-1 I²C master demultiplexer with an arbiter function. It is designed for high reliability dual master I²C-bus applications where correct system operation is required, even when two I²C-bus masters issue their commands at the same time. The arbiter will select a winner and let it work uninterrupted, and the losing master will take control of the I²C-bus after the winner has finished. The arbiter also allows for queued requests where a master requests the downstream bus while the other master has control. A race condition occurs when two masters try to access the downstream I²C-bus at almost the same time. The PCA9641 intelligently selects one winning master and the losing master gains control of the bus after the winning master gives up the bus or the reserve time has expired. Multiple transactions can be done without interruption. The time needed for multiple transactions on the downstream bus can be reserved by programming the Reserve Time register. During the reserve time, the downstream bus cannot be lost. Software reset allows a master to send a reset through the I²C-bus to put the PCA9641’s registers into the power-on reset condition. The Device ID of the PCA9641 can be read by the master and includes manufacturer, device type and revision. When there is no activity on the downstream I²C-bus over 100 ms, optionally the PCA9641 will disconnect the downstream bus to both masters to avoid a lock-up on the I²C-bus. The interrupt outputs are used to provide an indication of which master has control of the bus, and which master has lost the downstream bus. One interrupt input (INT_IN) collects downstream information and propagates it to the two upstream I²C-buses (INT0 and INT1) if enabled.

• 2-to-1 bidirectional master selector
• Channel selection via I²C-bus
• I²C-bus interface logic; compatible with SMBus standards
• 2 active LOW interrupt outputs to master controllers
• Active LOW reset input
• Software reset
• Four address pins allowing up to 112 different addresses
• Arbitration active when two masters try to take the downstream I²C-bus at the sametime
• The winning master controls the downstream bus until it is done, as long as it is withinthe reserve time
• Bus time-out after 100 ms on an inactive downstream I²C-bus (optional)
• Readable device ID (manufacturer, device type, and revision)
• Bus initialization/recovery function
• Low R_on switches
• Allows voltage level translation between 1.8 V, 2.3 V, 2.5 V, 3.3 V and 3.6 V buses
• No glitch on power-up
• Supports hot insertion
• Software identical for both masters
• Operating power supply voltage